The present invention relates to a semiconductor switching circuit.
There have recently been developed complicated but highly sophisticated MOS semiconductor integrated circuits capable of processing both digital and analog signals, such as analog/digital converters, digital/analog converters, switching capacitor filters or CODEC. An analog circuit section of the semiconductor integrated circuit contains analog circuit components such as MOS switch capacitors, amplifier circuits and resistor networks. For realizing such a complicated but highly sophisticated semiconductor integrated circuit, it is required to improve the circuit characteristics of these analog circuit elements.
A circuit characteristic of a MOSFET used as a MOS switch of the analog circuit elements will be described.
FIG. 1 illustrates an n-channel MOSFET TR1 used as a MOS switch for transferring a signal charge stored in a capacitor C1 to a capacitor C2 according to a drive signal VG. The capacitors C1 and C2 are coupled between the drain of the MOS transistor TR1 and ground, and between the source of the transistor TR1 and ground, respectively. Parasitic capacitors CS1 and CS2 are respectively associated between the drain and the gate, and the source and the gate of the MOS transistor TR1.
It is assumed that, in the MOS switching circuit shown in FIG. 1, the capacitors C1 and C2 have been respectively charged up to voltages V1 and V2 where V1 is larger than V2 in their initial state. Under this condition, when a high level drive signal or gate voltage VG is applied to the gate of the MOS transistor TR1, the MOS transistor TR1 is rendered conductive and the charge stored in the capacitor C1 is transferred through the MOS transistor TR1 to the capacitor C2. After the charge transfer is completed, the gate voltage VG is set low and the MOS transistor TR1 is rendered nonconductive. In this case, if the capacitances of the capacitors C1 and C2 are equal to each other, the charge voltage across the capacitors C1 and C2 must be both (V1+V2)/2 at the completion of the charge transfer. In fact, however, the gate voltage VG is partially applied to the capacitors C1 and C2 through the nonlinear parasitic capacitors CS1 and CS2 on the MOS transistor TR1, so that a feedthrough error voltage VFC is superposedly applied to the capacitors C1 and C2. Accordingly, the charge voltages of the capacitors C1 and C2 are each given by [(V1+V2)/2+VFE]. That is, the charge voltages of teh capacitors C1 and C2 are offset by an amount of the feedthrough error voltage. The feedthrough phenomenon arises from the parasitic capacitances associated with the MOS transistor. In some types of process controls, the adverse influence by the feedthrough phenomenon is unavoidable. In a situation requiring a high precision circuit characteristic, some measure must be taken for suppressing the adverse influence by the feedthrough phenomenon.
FIGS. 2 and 3 show prior art semiconductor circuits including semiconductor switching circuits with function for suppressing the adverse influence by the feedthrough phenomenon.
A semiconductor circuit shown in FIG. 2 is a sample/hold circuit for sampling and holding an analog input signal from a signal generator 2 according to a drive signal CP. The sample/hold circuit is provided with an n-channel MOS transistor TR2 whose conduction state is controlled in accordance with the drive signal CP and charges a capacitor C3 with a charge voltage corresponding to the analog input signal, and an n-channel MOS transistor TR3 which has a source and drain coupled with a drain of the MOS transistor TR2 and a gate connected to receive an inverted drive signal CP. The MOS transistor TR2 receives an original drive signal CP via MOS inverters I1 and I2 at the gate and the MOS transistor TR3 receives the output signal CP from the MOS inverter I2 at the gate. In this circuit, a capacitor CS3 is associated between the gate and the drain of the MOS transistor TR2, and capacitors CS4 and CS5 are respectively associated between the gate and the source, and between the gate and the drain of the MOS transistor TR3. On the basis of this fact, the dimensions of the MOS transistors TR2 and TR3 are selected so that the capacitance of the capacitor CS3 is equal to the sum of the capacitances of the capacitors CS4 and CS5. With such a design of the switching circuit, if all of the parasitic capacitors CS3 to CS5 are of the linear type, the adverse influence on the charge voltage of the capacitor C3, which is caused by the feedthrough phenomenon in the MOS transistor TR2, may be offset by the feedthrough phenomenon in the MOS transistor TR3.
A semiconductor circuit shown in FIG. 3 is provided with an n-channel MOS transistor TR4 for generating an output signal VO corresponding to an input signal VIN in response to a drive signal CP, and a p-channel MOS transistor TR5 having a current path coupled in parallel with the current path of the MOS transistor TR4 and receiving at the gate a drive signal CP. In this circuit, an original drive signal CP is supplied to the gate of the MOS transistor TR4 through MOS inverters I3 and I4, and an inverted output signal CP is applied to the gate of the MOS transistor TR5. In this semiconductor circuit, the dimensions of the MOS transistors TR4 and TR5 are so selected that the parasitic capacitors between the gate and the source, and between the gate and the drain of the MOS transistor TR5 are equal to each other. The adverse influence on the source and drain potentials, which is caused by the feedthrough phenomenon occurring in the MOS transistor TR4 is canceled by the adverse influence caused by the feedthrough phenomenon occurring in the MOS transistor TR5.
The semiconductor circuits shown in FIGS. 2 and 3 employ drive signals CP and CP, which are out of phase and formed of the MOS transistors for driving the pair of MOS transistors TR2 and TR3 and the pair of the MOS transistors TR4 and TR5. It is estimated by the inventors in the present patent application that this will give rise to the following problems.
(i) A phase shift occurs between the drive signals CP and CP. PA1 (ii) Since a coupling capacitor is a parasitic capacitor associated between the input and output terminals of the MOS inverter, an undershoot component and an overshoot component will be contained in the drive signals CP and CP. PA1 (iii) All of the parasitic capacitors associated with the MOS transistor are of the nonlinear type. PA1 (iv) A feedthrough phenomenon takes place through the nonlinear capacitor formed between the gate and the channel of each of the MOS transistors TR2 and TR4 operating as switches.
The combined problems (i) to (iv) above exert an adverse influence on the switching circuit, so that the prior art semiconductor switching circuits may not sufficiently suppress the adverse influence of the feedthrough phenomenon and can not reduce the offset voltage to a sufficiently small value. Nevertheless, the adverse influence of the feedthrough phenomenon originates from the presence of the nonlinear parasitic capacitors-and the inventors in the present patent application found that the feedthrough error may vary depending largely on problems (i) and (ii) among the problems (i) to (iv).